1/4 rev. b structure silicon monolithic integrated circuit name of product dc-ac inverter control ic type ?? function ? 36v high voltage process ? 1ch control with full-bridge ? lamp current and voltage sense feed back control ? sequencing easily achieved with soft start control ? short circuit protection with timer latch ? under voltage lock out ? mode-selectable the operating or stand-by mode by stand-by pin ? for slave ic, synchronous operating with bd9215f/fv ? burst mode controlled by pwm and dc input ? output liner control by external dc voltage absolute maximum ratingsta = 25 parameter symbol limits unit supply voltage v cc 3 6 v bst pin bst 40 v sw pin sw 36 v bst-sw voltage difference bst-sw 15 v operating temperature range topr -40+85 storage temperature range tstg -55+150 maximum junction temperature tjmax +150 power dissipation pd 749 *1 (BD9898F) mw 1062 *2 (BD9898Fv) *1 pd derate at 6.0mw/ for temperature above ta = 25 (when mounted on a pcb 70.0mm70.0mm1.6mm) *2 pd derate at 8.5mw/ for temperature above ta = 25 (when mounted on a pcb 70.0mm70.0mm1.6mm) operating condition status of this document the japanese version of this document is the official specification. please use the translation version of this document as a reference to expedite understanding of the official version. if these are any uncertainty in translation version of this document, official version takes priority. parameter symbol limits unit supply voltage v cc 16.030.0 v bst voltage bst 5.037.5 v bst-sw voltage difference bst-sw 5.014.0 v driver frequency fout 30110 khz bct oscillation frequency f bct 0.051.00 khz for operation condition of supply voltage, please see note for use(4page), more information. www.datasheet.in
2/4 rev. b electric characteristics ta=25vcc=24vstb=uvlo=3.0v parameter symbol limits unit conditions min. typ. max. whole device operating current icc1 5.5 10 ma fout=60khz, fb=gnd, bst=open stand-by current icc2 60 140 a stand by control stand-by voltage h vsth 2 vcc v system stand-by voltage l vstl -0.3 0.8 v system uvlo block operating voltage (uvlo) vuvlo 2.16 2.25 2.34 v hesteresis width (uvlo) Svuvlo 0.085 0.110 0.135 v reg block reg output voltage vreg 7.35 7.50 7.65 v reg source current ireg 20 ma osc block rt pin voltage vrt 1.05 1.50 1.95 v soft start current iss 1.7 2.2 2.7 a ss operation start voltage vss_st 0.18 0.20 0.22 v ss term end voltage vss_ ed 1.35 1.50 1.65 v srt on resistance rsrt 85 170 bosc block bosc max voltage vbcth 1.94 2 2.06 v fbct=0.3khz bosc min voltage vbctl 0.4 0.5 0.6 v fbct=0.3khz bosc constant current ibct 1.35/brt 1.5/brt 1.65/brt a vbct=0.2v bosc frequency fbct 291 300 309 hz (brt=37.8k bct=0.047f) feed back block is threshold voltage 1 vis1 1.225 1.25 1.275 v is threshold voltage 2 vis2 vrefin vis1 v vref applying voltag e vs threshold voltage vvs 1.22 1.25 1.28 v is source current 1 iis1 0.9 a duty=2.2v is source current 2 iis2 40 50 60 a duty=0v is=1.0v vs source current ivs 0.9 a is comp detect voltage 1 viscomp 1 0.606 0.625 0.644 v vrefinR1.2 5v is comp detect voltage 2 viscomp2 0.50 v vrefin= 1v vref input voltage range vrefin 0.6 1.6 v no effect at vref1 .25v output block ln output sink resistance rsinkln 1.8 3.5 7.0 ln output source resistance rsourceln 4.5 9.0 18.0 hn output sink resistance rsinkh n 1.8 3.5 7.0 vbst-vsw=7.0v hn output source resistance rsourceln 4.5 9.0 18.0 vbst-vsw=7.0 v max duty max duty 46.0 48.5 49.5 % fout=60khz off period toff 100 200 400 ns drive output frequency fout 57.9 60 62.1 khz rt=21k timer latch block timer latch setting voltage vcp 3.88 4.0 4.12 v timer latch setting current icp 1.6 2.1 2.6 a comp block comp over voltage detect voltage vcomph 3.88 4.0 4.12 v vss 1.65v hysterisis width (comp) Svcomph 0.15 0.20 0.25 v ((synchronous block)) high voltage vct_synch 3.8 4.0 4.2 v low voltage vct_syncl 0.5 v ct_sync_out sink resistance rsync_out_sink 150 300 ct_sync_out source resistance rsync_out_source 300 400 high voltage input range vct_sync_in_h 2.5 vct_synch v low voltage input range vct_sync_in_l -0.3 1 v this product is not designed to be radiation-resistant. www.datasheet.in
3/4 rev. b package dimensions pin description block diagram lot no. BD9898Fv BD9898F sop28 (unit:mm) ssop-b28 (unit:mm) device mark pin no. pin name function 1pgnd ground for fet drivers 2ln2 nmos fet driver 3hn2 nmos fet driver 4sw2 lower rail voltage for hn2 output 5bst2 boot-strap input for hn2 output 6 ct_sync_in ct synchronous signal input pin 7 ct_sync_out ct synchronous signal output pin 8srt external resistor from srt t ort f or ad j ustin g the start-u p trian g le oscillator 9rt external resistor from rt t ognd f or ad j ustin g the trian g le oscillator 10 gnd ground 11 bct external capacitor from bct t ognd f or ad j ustin g the burst trian g le oscillator 12 brt external resistor from brt t ognd f or ad j ustin g the burst trian g le oscillator 13 duty control pwm mode and burst mode 14 stb stand-by switch 15 cp external capacitor from cp t ognd f or timer latch 16 vref reference voltage input pin f or error am p lifier 17 vs error amplifier input 18 is error amplifier input 19 fb error amplifier output 20 ss external capacitor from ss t ognd f or soft start control 21 comp over voltage detect pin 22 vcc supply voltage input 23 uvlo external under voltage lock out 24 reg internal regulator output 25 bst1 boot-strap input for hn1 output 26 sw1 lower rail voltage for hn1 output 27 hn1 nmos fet driver 28 ln1 nmos fet driver www.datasheet.in
4/4 rev. b p substrate parasitic diode gnd n p p resistance transistor (npn) other adjacent components parasitic diode (pinb) (pina) p gnd p substrate gnd n n b c e n n (pina) (pinb) parasitic diode gnd gnd parasitic diode c b e note for use . this product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings. once ic is destroyed, failure mode will be difficult to determine, like short mode or open mode. therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum ratings. . the circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. the standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. when it is used in between stb-uvlo diode short etc., the ic can operate vcc 9v. please refer to a technical note in detail. . mounting failures, such as misdirection or miscounts, may harm the device. . a strong electromagnetic field may cause the ic to malfunction. . the gnd pin should be the location within 0.3v compared with the pgnd pin. all pin (except bst1, bst2, hn1, hn2,) voltage should be under vcc voltage +0.3v . BD9898F, BD9898Fv incorporate a built-in thermal shutdown circuit (tsd circuit). the thermal shutdown circuit (tsd circuit) is designed only to shut the ic off to prevent runaway thermal operation. it is not designed to protect the ic or guarantee its operation of the thermal shutdown circuit is assumed. . when modifying the external circuit components, make sure to leave an adequate margin for external components actual value and tolerance as well as dispersion of the ic. . about the external fet, the parasitic capacitor may cause the gate voltage to change, when the drain voltage is switching. make sure to leave adequate margin for this ic variation. . under operating cp charge (under error mode) analog dimming and burst dimming are not operate. 10. under operating slow start control (ss is less than 1.5v), it does not operate timer latch. 11. by stb voltage, BD9898F, BD9898Fv are changed to 2 states. therefore, do not input stb pin voltage between one state and the other state (0.82.0v). 12. the pin connected a connector need to connect to the resistor for electrical surge destruction. 13. this ic is a monolithic ic which (as shown is fig-1) has p + substrate and between the various pins. a p-n junction is formed from this p layer of each pin. for example, the relation between each potential is as follows, (when gnd > pinb and gnd > pina, the p-n junction operates as a parasitic diode.) (when pinb > gnd > pina, the p-n junction operates as a parasitic transistor.) parasitic diodes can occur inevitably in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. accordin gly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin. fig-1 simplified structure of a bipolar ic www.datasheet.in
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